#SWEET16 WOZNIAK CODE#

Most of my C code will be run on Arduino compatible platforms - so that it can easily be explored.įor hardware schematics and pcb layout, I generally use EagleCAD 6.x - but I am slowly moving towards open source tools including KiCAD and the online pcb design package from easyEDA

#SWEET16 WOZNIAK SIMULATOR#

Neeman's 'Digital' simulator - which is an updated version of Logisim

Hardware simulation will be done using H. Throughout this project I will need to learn new techniques and use new tools. Target Use: Co-processor / Accelerator for accompanying TTL colour computer (Gigatron) Performance: Aiming for 12.5MHz clock frequency to have some interoperability with VGA video systems. Hardware: ALU based on 4-bit bitslice design. Instruction Format: 8-bit bytecode in IR 15:8 augmented by 8-bit payload in IR 7:0 Other Instructions: IN OUT SRA SLA CLA STC CLCĪddressing Modes: Immediate #N, Register Direct Rn, Register Indirect Indirect Autoincrement Indexed Mode (Rn+X), Symbolic Mode (PC +X)

Program Flow: CALL RET JMP BRA and conditional branching BGT BLT BNE BEQ BGE BLE Memory and Register Instructions: SET LD ST POP PUSH R0 is the accumulator, most ALU operations are on Accumulator and a RegisterĪdditional Registers: Program Counter PC, Instruction Register IRĪLU Instructions: ADD SUB INC DEC COM AND OR XOR Registers: 16 general purpose registers R0 to R15. Principle Technology: 5V TTL logic with conventional through-hole DIL packages wherever possibleĪddress bus: 16-bits - with possible extension to 24-bitsĪrchitecture: Von Neuman Accumulator-Registerīasic 2 stage pipeline allowing most instructions to complete in 1 clock cycle

#SWEET16 WOZNIAK SOFTWARE#

In summary, Suite-16 is an exploration of the knowledge space bounded by hardware, software and FPGA design. You can find my Github repository here: Suite-16 This is updated regularly to include all the latest Arduino code and sketches. Later on, when the machine is debugged and can run simple code - there will be applications to be written such as high level languages.

These will include the Instruction Set - Architecture or ISA, an assembler and a software simulator of the proposed machine. Part of the project aim is to become familiar with FPGA design and verilog programming - and what better way than to set the goal of a working computer system.Īs any computer is the co-ordinated interaction between hardware and software - there will be several key software deliverables needed to complete the design.

It will also likely contain FPGA prototypes with their supporting designs coded in verilog.

#SWEET16 WOZNIAK SERIES#

The main deliverable will be a 16-bit computer system designed and built from 7400 series TTL integrated circuits outlined in the next section below.įrom a hardware point of view this will include circuit schematics, pcb layouts, timing diagrams and test-bench programs. Suite-16 refers literally to the suite of deliverables needed to put together a working 16-bit computer system. The Suite-16 project will encourage me to explore the interactions of hardware, firmware and software - hopefully widening my horizons, learning new skills and achieving the goal of building a working TTL computer system. I have had a lifetime in hardware engineering but very little real exposure to firmware and software since my Z80 coding days in the 1980s. Suite-16 arose from my curiosity regarding how computers work.

Sweet16 wozniak